SPI Signal description and Timing Diagram :-  

The SPI has a 3-wire synchronous serial interface. Data communication is enabled with a Chip Select wire (CS). Data is transmitted with a 3-wire interface consisting of wires for serial data input (SDI), chip select input (CS) and serial clock    (SCK).Which description in following table and SPI data read cycle.

Each transmission starts with a rising edge of CS and ends with the falling edge. During transmission, commands and data are controlled by SPICLK and CS according to the following rules:

Description:

• Data received width is 16 Bit in one SPI chip select input.
• Time required between one SPI chip select to another SPI chip select is 1msec.
• It receives MSB data first and LSB  last .
• Clock polarity should be Low to High(L to H transition).
• To avoid any false condition in data receiving ,connect common ground between both master SPI module and slave SPI module.
• Data is sampled onfalling edgeof SPI clock and shifted at frisingedge of SPI clock.

Frequency Tuning address :

In 16 bit data ,SPI only used 10 Bit data and remaining 6 Bit data is set to zero.In 10 Bit data first 2 Bit are used for path selection(i.e.path bit) and remaining are used for frequency tuning (i.e Tune Bit)